module smg(rstn,clk,uart_data,seg_sel,seg_led);
input clk,rstn;
//input end_sig;
input [7:0] uart_data;
output [2:0] seg_sel;
output [7:0] seg_led;
reg [2:0]  seg_sel;
reg [7:0] seg_led;
reg [7:0] seg1,seg2;
reg [7:0] data;
reg [31:0] m;
reg clk_out1;
parameter _0=8'h3f,_1=8'h06,_2=8'h5b,_3=8'h4f,_4=8'h66,_5=8'h6d,_6=8'h7d,_7=8'h07,_8=8'h7f,_9=8'h6f;
//位选
always @(posedge clk)
begin
	if(!rstn)
	begin clk_out1<=0; m<=0; end
	else
	begin
		m<=m+1;
		if(m==24999) clk_out1<=~clk_out1;
		if(m==49999) begin clk_out1<=~clk_out1; m<=0; end
	end
end
always @(posedge clk_out1)
begin
	if(!rstn)
	seg_sel<=3'd7;
	else
	if(seg_sel==3'd6)
	seg_sel<=3'd7;
	else 
	seg_sel<=seg_sel-3'd1;
end


///////////////
//段选
always@(seg_sel)
begin
	begin
		data<=uart_data; 		//接收完成，数据赋值
		case (seg_sel)
		3'd7:seg_led<=seg1;
		3'd6:seg_led<=seg2;
		endcase
	end
	
end

always @(data[3:0])
begin
case(data[3:0])
		0:seg1<=_0;  
		1:seg1<=_1;
		2:seg1<=_2;
		3:seg1<=_3;
		4:seg1<=_4;
		5:seg1<=_5;
		6:seg1<=_6;
		7:seg1<=_7;
		8:seg1<=_8;
		9:seg1<=_9;
	endcase
end

always @(data[7:4])
begin
case(data[7:4])
		0:seg2<=_0;  
		1:seg2<=_1;
		2:seg2<=_2;
		3:seg2<=_3;
		4:seg2<=_4;
		5:seg2<=_5;
		6:seg2<=_6;
		7:seg2<=_7;
		8:seg2<=_8;
		9:seg2<=_9;
	endcase
end




endmodule

/*module smg
(
		input		    		 clk			,
		input   		       rstn			,
		
		
		input      [7:0]   uart_din	,
		
		output reg [2:0]   seg_sel		,
		output reg [7:0]   seg_led        
		
);


wire [3:0] data0;
wire [3:0] data1;

assign data0 = uart_din % 4'd10;
assign data1 = uart_din / 4'd10;

reg [7:0] num;

always @(posedge clk or negedge rstn)begin
       if(!rstn) begin 
		   num <= 8'b0;
		 end 
		 else if(data1)begin 
		        num[7:4] <= data1;
				  num[3:0] <= data0;
				  end 
		 else begin 
		        num[3:0] <= data0;
				  num[7:4] <= 4'd11;
			   end
end 

always @(posedge clk or negedge rstn)begin
       if(!rstn) begin 
		   num <= 8'b0;
		 end 
		 else begin 
		        num[7:4] <= data1;
				  num[3:0] <= data0;
				  end
end  

reg [15:0] m       ;
reg        clk_out ;	
always @(posedge clk or negedge rstn)begin 
       if(!rstn) begin 
		   m <= 16'd0;
			clk_out <= 1'b0;
       end 
	    else begin 
	      m <= m + 1'b1;
	      if(m == 24999)
	         clk_out <= ~clk_out;
		   else if(m == 49999)	
	         clk_out <= ~clk_out;
            m <= 16'd0;
		 end 
end 

always @(posedge clk_out or negedge rstn)begin
       if(!rstn)
		   seg_sel <= 3'd0;
		 else if(seg_sel == 3'd1)
		   seg_sel <= 3'd0;
		 else 
		   seg_sel <= seg_sel + 1'b1;
end 

reg [7:0] num_drip;

always@(posedge clk or negedge rstn)begin
      if(!rstn)
		  num_drip <= 8'd0;
		else begin 
         
			 case(seg_sel)
			  3'd0: begin num_drip <= num[7:4] ; end 
			  3'd1: begin num_drip <= num[3:0] ; end 
			  
			  endcase
			  end 
end 

always @(posedge clk or negedge rstn)begin
      if(!rstn)
		   seg_led <= 8'b0000_0000;
		else begin
	 	
		case(num_drip)
	  4'd0 : seg_led<=8'b0011_1111;
	  4'd1 : seg_led<=8'b0000_0110;
	  4'd2 : seg_led<=8'b0101_1011;
	  4'd3 : seg_led<=8'b0100_1111;
	  4'd4 : seg_led<=8'b0110_0110;
	  4'd5 : seg_led<=8'b0110_1101;
	  4'd6 : seg_led<=8'b0111_1101;
	  4'd7 : seg_led<=8'b0000_0111;
	  4'd8 : seg_led<=8'b0111_1111;
	  4'd9 : seg_led<=8'b0110_1111;
	  4'd10: seg_led<=8'b0011_1111;
	  4'd11: seg_led<=8'b0100_0000;
	  
	  default: seg_led<=8'b0000_0000;
	  endcase
	  end 
	end
endmodule
			 
*/








      	  
				  
			































 

